<<Inter-chip Wireless Interconnection Using Inductive Coupling>>
* 일 시 : 2008년 7월 22일화요일 16:00-
* 장 소 : 반도체공동연구소 설계연구관 도연홀
* 연 사 : Sangwook Han
3-D integration became a promising technology for effective integration of complex systems; Previously Systems-On-Chip (SOC) came into spotlight for integration, but integrating digital logics and analog circuits in the same die turned out to be inefficient in deep submicron process. Substituting for SOC, 3-D integration, which is manufacturing devices with various different processes and stacking them, enables more efficient integration in terms of yield and chip performance.
Diverse solutions have been investigated for the realizations of 3-D integration such as hardwire bonding, micro-bumping, Through-Substrate-Via (TSV). However these direct connection approaches have drawbacks of low speed or high cost. To resolve these problems, wireless interconnection methods have been presented such as capacitive coupling and inductive coupling method.
In this work, various methods have been investigated in order to minimize power consumption and maximize data rate of inductive interconnection.
Ph.D. Course, Electrical Engineering and Computer Science, University of Michigan, Ann Arbor
M.S. in Engineering, University of Michigan, Ann Arbor
B.S. in Engineering, Seoul National University
담당교수 : 전기컴퓨터공학부 정덕균 (문의 : 김은영, Tel. 880-1306 )