The main research topics in the Design Automation Lab. are SoC (System-on-a-Chip) design, hardware/software codesign, low power design, processor architecture, and design methodology. It involves software synthesis, task scheduling, and HW/SW trade-off for real-time system design. It also involves high-level synthesis, low power architecture, platform-based design, and efficient SoC design methodology. We are also working on reconfigurable processor architecture and memory systems using non-volatile memory.
Research Interests & Projects
Recently, we are mainly focusing on the following topics.
- NoC architecture
- Application mapping on NoC
- Reconfigurable architecture
- Non-volatile memory system
Journals & Patents
 J. Ahn, S. Hong, S. Yoo, O. Mutlu, and K. Choi, "A scalable processing-in-memory accelerator for parallel graph processing," International Symposium on Computer Architecture, June 2015.
 J. Ahn, S. Yoo, O. Mutlu, and K. Choi, "PIM-enabled instructions: A low-overhead, locality-aware processing-in-memory architecture," International Symposium on Computer Architecture, June 2015.
 J. Lee, J. Ahn, K. Choi, and K. Kang, "THOR: orchestrated thermal management of cores and networks in 3D many-core architectures," Asia and South Pacific Design Automation Conference, .Jan. 2015.
 K. Han, G. Lee, and K. Choi, "Software-level approaches for tolerating transient faults in a coarse-grained reconfigurable architecture," IEEE Transactions on Dependable and Secure Computing, Jul. 2014.
 J. Ahn and K. Choi, "LASIC: loop-aware sleepy instruction caches based on STT-RAM technology," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, May 2014.
 J. Lee, S. Seo, J.K. Paek, and K. Choi, "Configurable range memory for effective data reuse on programmable accelerators," ACM Transactions on Design Automation of Electronic Systems, Mar. 2014.
 S. Lee and K. Choi, "Critical-path-aware high-level synthesis with distributed controller for fast timing closure," ACM Transactions on Design Automation of Electronic Systems, Mar. 2014.
 M. Jo, D. Lee, K. Han, and K. Choi, "Design of a coarse-grained reconfigurable architecture with floating-point support and comparative study," Integration, the VLSI Journal, Mar. 2014.