Faculty/Research

Research Groups

반도체 소자 연구실

Device Research Lab.

Prof. : Prof. Shin, Hyungcheol

Research Area : Semiconductor Devices & Integrated Circuits



  • About the Laboratory & Research Area
  • In the Device Research Laboratory, the characteristic analyses on nano-scale semiconductor devices such as Logic and memory device are actively implemented for large-impact research results. Device characteristics & reliability analyses in next-generation FinFET device and leakage current components & RTN phenomenon in DRAM cell transistor are analyzed. These researches provide the insights for device performance improvement as well as the understanding of device characteristics and reliability issues in Logic and memory devices.

    ▶ Research Areas
    1. Semiconductor device research (FinFET, DRAM, Random Telegraph Noise)
    2. Device modeling & characterization (AC/DC modeling, Device measurement & simulation)
  • Research Interests & Projects
  • ▶ Recent Interests
    - FinFET – Reliability and characterization analysis and 3D simulation
    - DRAM – Next generation DRAM device (BCAT, SRCAT) analysis/simulation
    - Device/Circuit Noise - (Flicker, RTN, Thermal) Noise modeling/analysis

    ▶ Main research projects
    - Design of Nano-belt transistor under 5 nm node and reliability analysis in 7 nm node device
    - VRT (Variable Retention Time) modeling under 20 nm node DRAM cell transistor
  • Journals & Patents
  • [1] Sung-Won Yoo, Joonha Shin, Youngsoo Seo, Hyunsuk Kim, Sangbin Jeon, Hyunsoo Kim, Hyungcheol Shin, “Characterizing traps causing random telegraph noise during trap-assisted tunneling gate-induced drain leakage”, Solid-State Electronics, vol. 109, no.7, pp. 42-46, Jul. 2015.
    [2] Hyunsoo Kim, Youngsoo Seo, and Hyungcheol Shin, "Extraction of Average Interface Trap Density using Capacitance-Voltage Characteristic at SiGe p-FinFET and Verification using Terman’s Method", Journal of The Institute of Electronics and Information Engineers, Vol. 52, no.4, pp. 668-673, Apr. 2015.
    [3] Duckseoung Kang, Kyunghwan Lee, Myounggon Kang, Seongjun Seo, Dong Hua Li, Yuchul Hwang, and Hyungcheol Shin, “Probability Level Dependence of Failure Mechanisms in Sub-20 nm NAND Flash Memory”,IEEE Electron Device Letters, Vol. 35, no. 3, pp. 348-350, Mar. 2014.
    [4] Quan Nguyen Gia, Sung-Won Yoo, Hyunseul Lee, Hyungcheol Shin, “Dependence on an oxide trap’s location of random telegraph noise (RTN) in GIDL current of n-MOSFET”, Solid-State Electronics, vol. 92, no. 2, pp. 20-23, Feb. 2014.
    [5] Kyunghwan Lee, Myounggon Kang, Seongjun Seo, Duck-Seoung Kang, Dong Hua Li, Yuchul Hwamg, and Hyungcheol Shin, “Separation of Corner Component in TAT Mechanism in Retention Characteristics of Sub 20-nm NAND Flash Memory,” IEEE Electron Device Letters, Vol. 35, No. 1, pp. 51-53, Jan. 2014.

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