Faculty/Research

Research Groups

컴퓨터이용설계 연구실

Computer-Aided Design Lab.

Prof. : Prof. Kim, Taewhan

Research Area : 컴퓨터 및 VLSI 시스템



  • About the Laboratory & Research Area
  • The sprit of our lab is to learn the ways of finding important problems, formulating the problems systematically and solving them efficiently. The scope of the problems covers both hardware (from system down to the circuit level) synthesis and optimizations and embedded software (compiler, operating system) optimizations. Computational and optimization theory is one essential feature for the research in System Synthesis Lab.
  • Research Interests & Projects
  • (참고: http://ssl.snu.ac.kr/main/doku.php/researcharea)3D IC Design
    3D physical design  
    3D clock path synthesis  
    3D power network delivery
    Flip-chip router, 3D timing analysis  
    3D thermal analysis and management  
    Reliable and Variation-Aware Design
    Process variation-aware HLS and system-level design  
    Power gating-aware HLS and logic design  
    Clock tree generation with noise minimization  
    NBTI-aware design  
    Embedded Software, Hardware
    Compilation techniques: Leakage power aware instruction generation
    Software platform design for multimedia/wireless applications
    Simulation and GUI environment tool for reconfigurable processor
    Code generation technique for leakage cache power minimization
    Multi-banks code access optimization
    DRAM memory access code optimization
    Address code generation for DSP-oriented processors
    Low-energy variable partitioning/scheduling for embedded processor with multiple banks
    Low-energy task/voltage scheduling (OS) for real-time embedded systems
    Data arrangements in DRAMs for access optimization
    Cache activity optimization for hard real-time embedded systems
    Low-power resource constrained bus encoding
    Voltage scheduling and allocation
    Access code optimization for embedded systems with multiple banks
    Low-energy code compression
         
    Thermal-Aware Design
    Thermal simulator tool
    Thermal-aware floorplanning
    Thermal-aware architecture/logic synthesis
    Logic synthesis for leakage current minimization
    Voltage island
    Architecture-Level Synthesis for System-on-Chip design
    Leakage-aware bus encode
    Interconnect/coupling-aware synthesis
    Unified (fabric-driven) synthesis and placement
    ALU design and arithmetic optimization
    Synthesis for low-power design architecture
    Leakage power optimization
         
    Logic-Level Synthesis
    Variation-aware false path analysis
    Synthesis/analysis for low-power logic circuit
    System (interface) synthesis
         
    High-Level Synthesis
    High-level synthesis for 3D IC design
    Synthesis for low power
    Memory synthesis
    Scheduling/allocation/testability for timing/area
  • Journals & Patents
  • [1] Heechun Park and Taewhan Kim, "Synthesis of TSV Fault-Tolerant 3D Clock Trees," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 34, No. 2, pp. 266-279, February 2015.
    [2] Minseok Kang and Taewhan Kim, "Integrated Resource Allocation and Binding in Clock Mesh Synthesis," ACM Transactions on Design Automation of Electronic Systems, Vol. 19, No. 3, pp. 30:1-30:28, June 2014.
    [3] Sangdo Park and Taewhan Kim, "Edge Layer Embedding Algorithm for Mitigation On-Package Variation in 3D Clock Tree Synthesis," Integration, the VLSI Journal, Vol. 47, No. 4, pp. 476-486, September 2014.
    [4] Byunghyun Lee and Taewhan Kim, "Algorithms for TSV Resource Sharing and Optimization in Designing 3D Stacked ICs," Integration, the VLSI Journal, Vol. 47, No. 2, pp. 184-194, March 2014.
    [5] Deokjin Joo and Taewhan Kim, "A Fine-Grained Clock Buffer Polarity Assignment for High-Speed and Low-Power Digital Systems,", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 33, No. 3, pp. 423-436, March 2014.
    [6] Kyoung-Hwan Lim, Deokjin Joo, and Taewhan Kim, "An Optimal Allocation Algorithm of Adjustable Delay Buffers and Practical Extensions for Clock Skew Optimization in Multiple Power Mode Designs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 3, pp. 392-405, March 2013.
    [7] Tak-Yung Kim and Taewhan Kim, "Resource Allocation and Design Techniques of Pre-bond Testable 3D Clock Tree," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 1, pp. 138-151, January 2013.
    [8] Jongyoon Jung and Taewhan Kim, "Statistical Viability Analysis for Detecting False Paths under Delay Variation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 1, pp. 111-123, January 2013.
    [9] Deokjin Joo, Minseok Kang, and Taewhan Kim, "Design Methodologies for Reliable Clock Networks," Journal of Computing Science and Engineering, Vol. 6, No. 4, pp. 257-266, December 2012.
    [10] Hyungjung Seo, Jaewon Seo, and Taewhan Kim, "Algorithms for Combined Inter- and Intra-Task Dynamic Voltage Scaling," The Computer Journal, Vol. 55, No. 11, pp. 1367-1382, November 2012.

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