ISDL has studied on various VLSI designs, especially, focusing on high-speed communication system. First, we are mainly working on high-speed I/O interfaces such as an optical link and a graphic interface. Next, we are also interested in capacitive sensing circuits such as a digital microphone and a touch screen controller. Recently, power ICs, which convert supply voltage level according to applications, are also studied. These power circuits mainly target LED driver unit. Finally, we have a research on transceiver for RF module and All-digital PLL replacing analog blocks with digital blocks to overcome difficulty of analog circuit design in DSM technologies.
J.-E. Park, D.-H. Lim, and D.-K. Jeong, “A Reconfigurable 40-to-67 dB SNR, 50-to-6400 Hz Frame-Rate, Column-Parallel Readout IC for Capacitive Touch-Screen Panels”, IEEE Journal of Solid-State Circuits, vol. 49, no. 10, pp. 2305–2318, 2014.
W. Kim, J. Park, H. Park, and D.-K. Jeong, “Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator,” IEEE Journal of Solid-State Circuits, vol. 49, no. 3, pp. 657-672, 2014.
S. Jang, S. Kim, S.-H. Chu, G.-S. Jeong, Y. Kim, and D.-K. Jeong, “An All-Digital Bang-Bang PLL Using Two-Point Modulation and Background Gain Calibration for Spread Spectrum Clock Generation,” in IEEE Symposium on VLSI Circuits, 2015, pp. 136-137
S.-H. Chu, W. Bae, G.-S. Jeong, J. Joo, G. Kim, and D.-K. Jeong, “A 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in 65nm CMOS Process”, in IEEE Asian Solid-State Circuits Conference, 2014, pp. 101-104.
H.-K. Chi, T.-S. Song, S.-M. Ye, G.-M. Hong, W.-R. Bae, M.-S. Chu, D.-K. Jeong, S.-H. Kim, “Receiver, system including the same, and calibration method thereof,” US 9059825, 2015.
M.-S. Hwang, W.-J. Choe, H.-K. Chi, and D.-K. Jeong, “Coarse Lock Detector,” US 9000814, 2015.