Emerging Deep-Learning Chip Architecture
일시 : 2019년 7월 30일(화), 16:00 ~ 17:00
장소 : 서울대학교반도체공동연구소설계관(104-1동) 도연홀(301호)
연사 : Mingoo Seok
Computing technology has been the backbone of our society. Its importance is hard to overemphasize. Today, we again confirm its extreme importance with recent advances in artificial intelligence and deep learning. Those emerging workloads impose an unprecedented amount of arithmetic complexity and data access beyond our existing computing systems can barely handle. Across the computing systems from data centers, to mobile, and to extreme implants will face a major challenge in achieving desirable speed, energy-efficiency, and accuracy for truly enabling intelligent systems. In this seminar, we will outline the important bottlenecks to designing computing hardware for deep learning, which include i) a very large amount of arithmetic complexity and ii) the memory wall problem. We will then discuss several approaches that our group has been working on, including in-memory computing SRAM, in-memory computing DRAM, digital multi-core spatial array accelerator, and hybrid analog-digital computing hardware. We will introduce several test-chip prototypes and their measurement results.
Mingoo Seok is an associate professor of Electrical Engineering at Columbia University. He received the BS from Seoul National University, South Korea, in 2005, and the MS and Ph.D. degree from the University of Michigan in 2007 and 2011, respectively, all in electrical engineering. His research interests are various aspects of VLSI circuits and architecture, including ultra-low-power integrated systems, cognitive and machine-learning computing, adaptive technique for the process, voltage, temperature variations, and transistor wear-out, integrated power management circuits, event-driven controls, and hybrid continuous and discrete computing. He won the 2015 NSF CAREER award and 2019 Qualcomm Faculty Award. He is the technical program committee members for multiple conferences including IEEE International Solid-State Circuits Conference (ISSCC). He has been as an associate editor for IEEE Transactions on Circuits and Systems Part I (TCAS-I) (2014-2016), IEEE Transactions on VLSI Systems (TVLSI) (2015-present), IEEE Solid-State Circuits Letter (SSCL) (2017-present), and as a guest associate editor for IEEE Journal of Solid-State Circuits (JSSC) (2019).
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