[세미나] Minimum Energy Operation and Time-dependent Variability in Scaled CMOS Process

2019-03-26l Hit 1111

 Minimum Energy Operation and Time-dependent Variability in Scaled CMOS Process


 Prof. Hidetoshi Onodera

연사 : Prof. Hidetoshi Onodera (Kyoto University) 
일시 : 2019년 3월 29일 (금) 16:00~18:00
장소 : 신공학관 301동 620호



Talk 1: Minimum Energy Operation of Voltage-Scaled Circuits
  There is a set of supply voltage (Vdd) and threshold voltages (Vthn and Vthp), which is called "Minimum Energy Point (MEP)," that leads to the minimum energy consumption per operation under a specified timing constraint.

  First, simulated MEP loci in a Vdd-Vth space will be shown for a model circuit and a processor. The shape of the locus suggest us an effective strategy for DVFS and ABB. Then a measured MEP locus of an on-chip memory will be explained together with the standard-cell based structure of the memory for stable operation under a lower supply voltage for reducing energy consumption.

  Next, an algorithm for MEP tracking will be introduced. MEP operation requires information on operating conditions such as Vth and temperature together with threshold-voltage control capability. Ring-oscillator-based on-chip monitors and a body-bias-generator compatible with cell-based design will be discussed.


Talk 2: Time-dependent variability in scaled CMOS process
  In addition to the conventional PVT (Process, Voltage and Temperature) variation, time-dependent current fluctuation such as random telegraph noise (RTN) poses a new challenge on VLSI reliability.

  In this talk, it is shown that RTN amplitude of a particular device is not constant across supply voltages and temperatures. As a result, RTN amplitude distribution becomes uncorrelated across a wide range of voltage and temperature. The emergence of uncorrelated distribution causes significant degradation of worst-case values. Delay variation analysis shows that consideration of RTN in the statistical analysis have little impact at high supply voltage. However, at low voltage operation, RTN can degrade the worst-case value by more than 5 %.


  Hidetoshi Onodera received the B.E., and M.E., and Dr. Eng. degrees in Electronic Engineering, all from Kyoto University, Kyoto, Japan. He joined the Department of Electronics, Kyoto University, in 1983, and currently a Professor in the Department of Communications and Computer Engineering, Graduate School of Informatics, Kyoto University. His research interests include design technologies for Digital, Analog, and RF LSIs, with particular emphasis on low-power design, design for manufacturability, and design for dependability.

  Dr. Onodera served as the Program Chair and General Chair of ICCAD and ASPDAC. He was the Chairman of SSCS Kansai Chapter, IEEE CASS Kansai Chapter, and IEEE Kansai Section, and the Vice President of Awards in IEEE CEDA Executive Committee. He served as the Editor-in-Chief of IEICE Transactions on Electronics and IPSJ Transactions on System LSI Design methodology. He is an IEEE Fellow, an IEICE Fellow, and a Member of Science Council of Japan.


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