Machine Learning in Electronic Design Automation: Opportunities and Value Propositions
■ 연사 : Prof. Andrew B. Kahng (UC San Diego CSE and ECE Departments)
■ 일시 : 2017년 9월 7일 (목) 16:00~17:20
■ 장소 : 신공학관 301동 202호
In the late-CMOS era, semiconductor and electronics companies face severe product schedule and other competitive pressures. In this context, electronic design automation (EDA) must deliver "design-based equivalent scaling" to help continue essential industry trajectories. A powerful lever for this will be the use of machine learning techniques, both inside and "around" EDA tools. This talk will try to convey some key opportunities and value propositions for machine learning in EDA, supported by concrete existence proofs. Example topics include (1) achieving faster design convergence through new predictors of downstream flow outcomes, (2) removing unnecessary design and modeling margins through new correlation mechanisms, and (3) optimizing the usage of EDA tool licenses and available schedule.
OPTIONAL: "Quality, Schedule and Cost: The New (and Last) Semiconductor Scaling Levers"
Lateral scaling in semiconductor manufacturing and device architecture will be extremely challenging after the foundry 5nm/3nm nodes. Thus, continuing the Moore's-Law trajectory of value scaling will require new (and, final) levers. This talk will describe three basic types of these levers. The first lever is quality: improved design tools and methods must recover IC design quality that was left on the table as the industry rode scaling in the past decade's "race to the end of the roadmap". The second lever is schedule: the temporal axis of Moore's Law (i.e., "one week is one percent") must become a focus for delivery of new, "design-based equivalent scaling" value. The third lever is cost: new mechanisms must be found to reduce the cost of IC design infrastructure as well as the cost and difficulty of the IC design process itself.
Andrew B. Kahng is Professor of CSE and ECE at UC San Diego, where he holds the endowed chair in High-Performance Computing. He has served as visiting scientist at Cadence (1995-1997) and as founder/CTO at Blaze DFM (2004-2006). He is the coauthor of 3 books and over 400 journal and conference papers, holds 33 issued U.S. patents, and is a fellow of ACM and IEEE. He has served as general chair of DAC, ISQED, ISPD and other conferences. He served as international chair/co-chair of the Design technology working group, and of the System Integration focus team, for the International Technology Roadmap for Semiconductors (ITRS) from 2000-2016. His research interests include IC physical design and performance analysis, the IC design-manufacturing interface, combinatorial algorithms and optimization, and the roadmapping of systems and technology.
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