The teams of researchers “Yoo-hwan Shin, Yong-wu Jo, Jun-seok Lee, Jong-hwa Kim” and “Yun-seo Cho, Se-heon Jang, Seo-hi Jeong” of the Integrated Circuits and Systems Lab(ICSL) led by professor Jae-hyouk Choi were each awarded the Ministry of Trade, Industry and Energy Minister’s Award from this year’s 24th Korean Semiconductor Design Contest. The following list shows the awarded designs.
1. Orthogonal Signal Generator with Noise Filtering Effect for Ultra-low Signal Distribution in Next Generation High-speed DRAM Interfaces
2. Ring-type Voltage Controlled Oscillator-based High-speed Frequency Multiplier Fixed Loop for Next Generation High-speed Data Communication Clocks Using Power Gating Method
Translated by: Jiyong Yoo, English Editor of the Department of Electrical and Computer Engineering, firstname.lastname@example.org