커뮤니티 | Community

세미나

[세미나] [4과 세미나: 10월 29일] Delay modeling and power analysis of on-chip interconnects

2009-10-21l 조회수 10404




Delay modeling and power analysis of on-chip interconnects

 연사 : 김소영  (성균관대학교 정보통신공학부 반도체시스템전공 조교수)
 일시 : 2009년 10월 29일 (목) 오후 5:30~6:20
 장소 : 서울대학교 301동 118호

Abstract : As technology scales, interconnect parasitic effects are becoming increasingly significant, directly limiting circuit performance and wiring density. Due to higher clock frequencies, and lower resistivity copper interconnects, inductance can no longer be neglected in interconnect design. We will first look at various backend technologies that enabled technology scaling following the Moore\'s Law. Then we will look at standard steps in interconnect extraction and timing analysis, with emphasis on on-chip inductance effects.  
As technology scales and chip operating frequency increases, on-chip power density increases. In the second part of this talk, I will introduce on-chip power design automation and analysis using commercial EDA software.  I will talk about static power analysis and dynamic power analysis techniques and show how the various low power design techniques can be applied in the design based on dynamic power analysis results.

Biography: SoYoung Kim received her B.S. in Electrical Engineering from Seoul National University, Seoul, Korea in 1997. She received her M.S. and Ph.D. in Electrical Engineering from Stanford University, Stanford, California in 1999 and 2004 respectively. Her Ph.D. thesis title is “Modeling and Screening On-Chip Interconnect Inductance”. From 2004 to 2008, she worked as a senior CAD engineer at Intel Corporation, Santa Clara, California, developing capacitance models and providing backend technology support. From 2008 to 2009, she worked as a member of consulting staff at Cadence Design Systems, San Jose, California, developing Encounter Power System (Power analysis tool) focusing on gate-level power estimation. Since March, 2009, she is with the Department of Semiconductor Systems Engineering at SungKyunKwan University in Suwon, Korea. Her research interests are VLSI power and thermal analysis, Interconnect analysis, 3DIC’s, and low power SOC’s.


--------------------------------------------------------------------------------------------------------------------------------
전기공학부 홈페이지 : http://ee.snu.ac.kr/                              정보기술 사업단
담당교수 : 전기공학부 차상균                    문의 : 02) 874-7812   chask@snu.ac.kr

RELATED LINKS



학부연구실+ more  


TOP