Characterization of Process Variability and Robust Optimization
of High-Speed Analog Building Blocks
일 시 : 2008년 9월 10일 수요일 11:00-12:00
장 소 : 서울대학교 반도체공동연구소 설계연구관 도연홀
연 사 : 임대현
Continuous scaling of CMOS technology has enabled dramatic performance enhancement of CMOS devices and has provided speed, power, and density improvement in both digital and analog circuits. CMOS millimeter-wave applications operating at more than 50GHz frequencies has become viable in sub-100nm CMOS technologies, providing advantages in cost and high density integration compared to other heterogeneous technologies such as SiGe and III-V compound semiconductors.
However, as the operating frequency of CMOS circuits increases, it becomes more difficult to obtain sufficiently wide operating ranges for robust operation in essential analog building blocks such as voltage-controlled oscillators (VCOs) and frequency dividers. The fluctuations of circuit parameters caused by the random and systematic variations in key manufacturing steps become more significant in nano-scale technologies. The process variation of circuit performance is quickly becoming one of the main concerns in high performance analog design.
In this thesis, we show design and analysis of a VCO and frequency divider operating beyond 70GHz in a 65nm SOI CMOS technology.
The VCO and frequency divider employ design techniques enlarging frequency operating ranges to improve the robustness of circuit operation. Circuit performance is measured from a number of die samples to identify the statistical properties of performance variation.
A back-propagation of variation (BPV) scheme based on sensitivity analysis of circuit performance is proposed to extract critical circuit parameter variation using statistical measurement results of the frequency divider.
We analyze functional failure caused by performance variability, and propose dynamic and static optimization methods to improve parametric yield. An external bias control is utilized to dynamically tune the divider operating range and to compensate for performance variation. A novel time delay model of a differential CML buffer is proposed to functionally approximate the maximum operating frequency of the frequency divider, which dramatically reduces computational cost of parametric yield estimation. The functional approximation enables the optimization of the VCO and frequency divider parametric yield with a reasonable amount of simulation time.
Daihyun Lim received the B.S. degree in electrical engineering from Seoul National University, Korea, in 1999, and the S.M. and PhD degrees in electrical engineering and computer science from Massachusetts Institute of Technology in 2004, and 2008, respectively.
His research interest is Design for Manufacturability (DFM) for high speed analog circuits, including the modeling of process variation in analog circuit parameters and efficient design techniques to optimize circuit performance against the variability.
담당교수 : 전기컴퓨터공학부 정덕균 (문의 : 김은영, Tel. 880-1306 )