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[세미나] [ESRC] Adaptive Bandwidth Techniques for Low-Jitter Clock Generation and Clock/Data Recovery

2004-06-10l 조회수 15727




안녕하세요. 내장형시스템연구센터(ESRC)입니다.
다음 주 월요일에(6월 14일) 저희 ESRC에서 아래와 같이 세미나를 준비하였습니다.
여러분들의 많은 관심과 참여를 부탁드립니다.

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◆ 일시 : 2004. 6. 14 (월) 오전 11시 - 12시

◆ 장소 : 반도체공동연구소 설계연구관 도연홀

◆ 주제 : Adaptive Bandwidth Techniques for Low-Jitter Clock Generation and Clock/Data Recovery

◆ 강사 : Prof. Gu-Yeon Wei (Harvard University)

◆ Abstract
Low-jitter clock generation and clock/data recovery (CDR) blocks are important components required for reliable operation of high-speed synchronous systems such as microprocessors and data communication links. These blocks must contend with several noise sources that can adversely impact performance. This talk presents a mixed PLL/DLL architecture for low-jitter clock generation and to be used as a core component for clock/data recovery. This architecture merges the characteristics of PLLs and DLLs via an interpolator in order to easily adjust loop dynamics in response to different noise environments.


◆ Biography
1994 - B.S. Degree in the Stanford University
1997 - M.S. Degree in the Stanford University
2001 - Ph.D. Degree in the Stanford University
2001 - Senior Design Engineer at Accelerant Networks in Beaverton, Oregon
2002 - Assistant Professor of Electrical Engineering in the Division of Engineering and Applied Sciences of Harvard University

Current Research Interest: mixed-signal VLSI circuits and systems design for high-speed/low-power wireline data communication, low-jitter clock generation, energy-efficient computing devices for sensor networks, and biosensor applications

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세미나 문의
김소영 (Tel: 880-1310 / E-mail: sykim@esrc.snu.ac.kr)

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