반도체공동연구소 세 미 나
" Recent Technology &Trends in Dielectric Etch "
◈ 일시 : 2003년 11월 27일 오후 4시 30분 - 5시 30분
◈ 장소 : 서울대학교 반도체공동연구소 설계연구관 도연홀
◈ 연사 : Dr. Jong W. Shon (Lam Research Corp.)
Dielectric etch technology is dictated by ever-shrinking feature size of semiconductor devices and delicate materials used in its fabrication. Specially material issues are difficult to overcome, for example, porous low k material for logic devices and 193nm ArF photoresist for all devices. Main etchers for three primary manufacturers now use dual frequency RIE technology for its inherent uniformity and independent control of ion energy and flux. In this presentation, current challenges in dielectric etch and latest etcher technology will be discussed.
Ph.D. Electrical &Computer Engineering (10/93), University of Illinois, Urbana, IL
M.S. Electrical &Computer Engineering, University of Illinois, Urbana, IL
B.S. Electrical &Computer Engineering with highest honor, Oregon State University
B.S. Mathematics with highest honor, Oregon State University, Corvallis, OR
B.S. Computer Science with highest honor, Oregon State University, Corvallis, OR
10/99 Lam Research Corporation, Fremont, CA - Sr. Staff Scientist
3/97-10/99 Lawerence Livermore National Laboratories, Livermore, CA
10/96 P&S Associates, Palo Alto, CA - Senior Research Scientist
10/93 Sandia National Laboratories, Livermore, CA
Thermal and Plasma Processes Department