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[세미나] [ESRC] Design For Excellence (DFX) for Complex ASICs or SOCs

2003-11-17l 조회수 15978




내장형시스템연구센터(ESRC)에서 아래와 같이 세미나를 준비하였습니다.
Cisco Systems의 Douglas Kay 박사께서 "Design For Excellence (DFX) for Complex ASICs or SOCs"에 관하여 강의를 하십니다.
관심있는 분들의 많은 참석을 부탁드립니다.

-------------------------------     아       래     ---------------------------------
1. 일시 : 2003. 11. 25 (화) 오후 4시
2. 주제 : Design For Excellence (DFX) for Complex ASICs or SOCs
3. 강사 : Douglas Kay (Cisco Systems)
4. 장소 : 반도체공동연구소 설계연구관 도연홀 (104-1동)
5. Abstract :
     In introduction, the presenter will review the principles of IC testing    
    (Digital emphasis)  interacting with the audience. Then, update of the  
    status of DFX techniques in the  industry for complex and advanced chip
    designs or SOCs. Will discuss various  research topics which may
    become important in the coming years.
6. 강연자 약력
    B.S in SNU (Electrical Engineering)
    M.S in Univ. of Southern California (Computer Engineering)
    Ph.D in Santa Clara University (Electrical Engineering)
    현재 ;
    ASIC DFX Technologist and Project Manager in Cisco Systems.
    Adjunct faculty of Santa Clara University
    Research member of ASIC Testing Lab.
    IEEE standard working group task force member for IEEE P1500 (CTAG) and P1450.6 (CTL)
    Korea IT Network (KIN) Technology 2003 Conference Chair
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담당/문의 : 김소영 (880-1309/sykim@esrc.snu.ac.kr)

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