[세미나] [ISRC-BK21세미나]▶Multicore challenges:scalability, security and performance predictability◀
<<Multicore challenges : scalability, security and performance predictability>>
* 일 시 : 2008년 7월 22일화요일 13:30-14:30
* 장 소 : 서울대학교 반도체공동연구소 설계연구관 도연홀
* 연 사 : Jae W. Lee
Small-scale multicore processors are already widely used in mainstream desktops, servers as well as mobile devices. However, many research challenges are yet to be addressed for designing and programming future manycore processors. In this talk, I will selectively present my past and current work addressing such challenges (in reverse chronological order) to improve the scalability, security and performance predictability in future manycore platforms.
To achieve better performance predictability in multi-hop on-chip networks, which are an important component in future manycore processors, we propose globally synchronized frames (GSF) to provide guaranteed quality-of-service (QoS) to each thread [ISCA \'08]. For security, I will discuss two techniques. First, I will describe how to build a secret key (i.e., unique fingerprint) to each chip exploiting the statistical delay variations of wires and transistors across ICs [SOVC \'04]. Second, I will present an architectural mechanism to thwart buffer overflow attacks, which are one of the most common methods for malicious intruders to obtain unauthorized accesses to a system, called dynamic information flow tracking [ASPLOS \'04]. If time permits, I will briefly overview the motivation and implementation of the Raw microprocessor from MIT to overcome the scalability problem of conventional superscalar processors [IEEE Micro \'02].
Jae W. Lee is a PhD candidate in Computer Science under Prof. Asanovic and Prof. Arvind at MIT and a member of Computer Science and Artificial Intelligence Lab (CSAIL). He is currently visiting the Parallel Computing Laboratory (Par Lab) at the University of California, Berkeley, as a graduate exchange scholar.
He received his bachelor\'s degree from Seoul National University, South Korea, and master\'s degree from Stanford both in electrical engineering. His research interests are computer architecture and VLSI design. Currently, he is focusing on resource management in chip multiprocessors particularly in on-chip networks and memory hierarchy. He has strong interests in architectural prototyping thorough FPGA and/or custom ASIC. He led the first ASIC implementation of physical uncloneable function, or PUF, at MIT and also contributed to development of the Raw Microprocessor at MIT and the Media Control Processor (MCP) in NForce2 chipset at NVidia as a summer intern.
* Homepage: http://people.csail.mit.edu/leejw/
담당교수 : 전기컴퓨터공학부 정덕균 (문의 : 김은영, Tel. 880-1306 )